The present invention relates generally to methods for forming integrated circuit chips, and more particularly, to a method for simplifying the processing of core and periphery isolation regions.
An integrated circuit chip comprises an array of devices formed in a semiconductor substrate, with the contacts for these devices interconnected by patterns of conductive wires. As the density of devices fabricated on a given chip increases, problems arise in providing reliable isolation between devices. Additionally, the core area on a chip may utilize different device dimensions than the periphery area on the chip. These different device dimensions necessarily require different isolation techniques which further complicate the processing of the overall chip.